Difference between revisions of "Instruction Set/mulswv"
From Mill Computing Wiki
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| − | + | Signed integer multiply. Widening for a vector. | |
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<code style="font-size:130%"><b style="color:#050">mulswv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code> | <code style="font-size:130%"><b style="color:#050">mulswv</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#s|s]] r<sub>0</sub>, [[Domains#s|s]] r<sub>1</sub></code> | ||
Revision as of 18:53, 20 December 2014
realizing exu stream exu block compute phase operation in the signed integer value domain using widening overflow behavior that produces condition codes
native on: all
Signed integer multiply. Widening for a vector.
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Copper | E0 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Silver | E0 E1 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Gold | E0 E1 E2 E3 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Decimal8 | E0 E1 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
| Decimal16 | E0 E1 | bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
