Difference between revisions of "Instruction Set/narrowffz"

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{{DISPLAYTITLE:narrowffz}}
 
{{DISPLAYTITLE:narrowffz}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Rounding|and rounds to nearest, ties away from zero]]<br />
 
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
 
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
 
</div>
 
</div>

Revision as of 18:52, 20 December 2014

realizing  exu stream  exu block  compute phase   operation   in the binary floating point value domain   and rounds to nearest, ties away from zero

native on: Silver Gold

narrow scalar to half width


narrowffz(f v) → f r0

operands: like Narrowf [ff:½f]


Core In Slots Latencies
Silver E0 E1 w:h=3 d:w=4 q:d=5
Gold E0 E1 E2 E3 w:h=3 d:w=4 q:d=5

narrowffz(f v1, f v2) → f r0

operands: like Narrowvf [FF:½F]


Core In Slots Latencies
Silver E0 E1 wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5
Gold E0 E1 E2 E3 wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5


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