Difference between revisions of "Instruction Set/mulfp"

From Mill Computing Wiki
Jump to: navigation, search
Line 1:Line 1:
 
{{DISPLAYTITLE:mulfp}}
 
{{DISPLAYTITLE:mulfp}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward positive infinity]]<br />
 
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
 
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
 
</div>
 
</div>

Revision as of 18:51, 20 December 2014

realizing  exu stream  exu block  compute phase   operation   in the binary floating point value domain   that produces condition codes and rounds toward positive infinity

native on: Silver Gold

Floating point multplication in current rounding towards positive infinity.


mulfp(f x, f y) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1 w,w:w=4 wv,wv:wv=4 d,d:d=5 dv,dv:dv=5 q,q:q=6 qv,qv:qv=6
Gold E0 E1 E2 E3 w,w:w=4 wv,wv:wv=4 d,d:d=5 dv,dv:dv=5 q,q:q=6 qv,qv:qv=6


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable