Difference between revisions of "Instruction Set/exuArgs"

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additional slot for ganged exu operation
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Additional arguments for [[Gang]]ed operations.
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All data paths for the operands of compute operations are optimized for 2 operands. Yet some operations need more. For those operations, like [[Instruction_Set/fmaf|fmaf]] or [[Instruction_Set/inject|inject]], a primary opcode in one [[Slot]] and the `exuArgs` opcode in the next together form the full operation with all operands.
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This is possible because neighboring [[Slot]]s and their [[Pipeline]]s can pass data between each other in a side path  without needing a full interconnecting data path.
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<code style="font-size:130%"><b style="color:#050">exuArgs</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">arg</span>)</code>
 
<code style="font-size:130%"><b style="color:#050">exuArgs</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">arg</span>)</code>

Revision as of 17:10, 16 December 2014

realizing  exu stream  exu block  compute phase   operation  

native on: all

Additional arguments for Ganged operations.

All data paths for the operands of compute operations are optimized for 2 operands. Yet some operations need more. For those operations, like fmaf or inject, a primary opcode in one Slot and the `exuArgs` opcode in the next together form the full operation with all operands.

This is possible because neighboring Slots and their Pipelines can pass data between each other in a side path without needing a full interconnecting data path.


exuArgs(op arg)

operands: like Inv :


Core In Slots Latencies
Tin E0 E1 0
Copper E0 E1 0
Silver E0 E1 E2 E3 0
Gold E0 E1 E2 E3 E4 E5 E6 E7 0
Decimal8 E0 E1 E2 E3 0
Decimal16 E0 E1 E2 E3 0

exuArgs(op arg0, op arg1)

operands: like Inv :


Core In Slots Latencies
Tin E0 E1 0
Copper E0 E1 0
Silver E0 E1 E2 E3 0
Gold E0 E1 E2 E3 E4 E5 E6 E7 0
Decimal8 E0 E1 E2 E3 0
Decimal16 E0 E1 E2 E3 0


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