Difference between revisions of "Instruction Set/wr"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:wr}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|writer block]...")
 
Line 14:Line 14:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#912|Tin]] || W0 W1 || 3
+
| [[Cores/Tin/Encoding#wr|Tin]] || W0 W1 || 3
 
|-
 
|-
−
| [[Cores/Copper/Encoding#912|Copper]] || W0 W1 || 3
+
| [[Cores/Copper/Encoding#wr|Copper]] || W0 W1 || 3
 
|-
 
|-
−
| [[Cores/Silver/Encoding#912|Silver]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Silver/Encoding#wr|Silver]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#912|Gold]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Gold/Encoding#wr|Gold]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#912|Decimal8]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Decimal8/Encoding#wr|Decimal8]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#912|Decimal16]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Decimal16/Encoding#wr|Decimal16]] || W0 W1 W2 W3 W4 || 3
 
|}
 
|}
  
Line 36:Line 36:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#913|Tin]] || W0 W1 || 3
+
| [[Cores/Tin/Encoding#wr|Tin]] || W0 W1 || 3
 
|-
 
|-
−
| [[Cores/Copper/Encoding#913|Copper]] || W0 W1 || 3
+
| [[Cores/Copper/Encoding#wr|Copper]] || W0 W1 || 3
 
|-
 
|-
−
| [[Cores/Silver/Encoding#913|Silver]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Silver/Encoding#wr|Silver]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#913|Gold]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Gold/Encoding#wr|Gold]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#913|Decimal8]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Decimal8/Encoding#wr|Decimal8]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#913|Decimal16]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Decimal16/Encoding#wr|Decimal16]] || W0 W1 W2 W3 W4 || 3
 
|}
 
|}
  
Line 58:Line 58:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#914|Tin]] || W0 W1 || 3
+
| [[Cores/Tin/Encoding#wr|Tin]] || W0 W1 || 3
 
|-
 
|-
−
| [[Cores/Copper/Encoding#914|Copper]] || W0 W1 || 3
+
| [[Cores/Copper/Encoding#wr|Copper]] || W0 W1 || 3
 
|-
 
|-
−
| [[Cores/Silver/Encoding#914|Silver]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Silver/Encoding#wr|Silver]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#914|Gold]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Gold/Encoding#wr|Gold]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#914|Decimal8]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Decimal8/Encoding#wr|Decimal8]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#914|Decimal16]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Decimal16/Encoding#wr|Decimal16]] || W0 W1 W2 W3 W4 || 3
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  exu stream  writer block  writer phase   operation   in the logical value domain  

native on: all

hardware writer

wr(scratch dst, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin W0 W1 3
Copper W0 W1 3
Silver W0 W1 W2 W3 W4 3
Gold W0 W1 W2 W3 W4 3
Decimal8 W0 W1 W2 W3 W4 3
Decimal16 W0 W1 W2 W3 W4 3

wr(reg dst, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin W0 W1 3
Copper W0 W1 3
Silver W0 W1 W2 W3 W4 3
Gold W0 W1 W2 W3 W4 3
Decimal8 W0 W1 W2 W3 W4 3
Decimal16 W0 W1 W2 W3 W4 3

wr(stream dst, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin W0 W1 3
Copper W0 W1 3
Silver W0 W1 W2 W3 W4 3
Gold W0 W1 W2 W3 W4 3
Decimal8 W0 W1 W2 W3 W4 3
Decimal16 W0 W1 W2 W3 W4 3


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/wr&oldid=2013"