Difference between revisions of "Instruction Set/mulswv"

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(Created page with "{{DISPLAYTITLE:mulswv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu block...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Tin/Encoding#607|Tin]] || E0 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
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| [[Cores/Tin/Encoding#mulswv|Tin]] || E0 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
 
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| [[Cores/Copper/Encoding#607|Copper]] || E0 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
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| [[Cores/Copper/Encoding#mulswv|Copper]] || E0 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
 
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| [[Cores/Silver/Encoding#607|Silver]] || E0 E1 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
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| [[Cores/Silver/Encoding#mulswv|Silver]] || E0 E1 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
 
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| [[Cores/Gold/Encoding#607|Gold]] || E0 E1 E2 E3 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
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| [[Cores/Gold/Encoding#mulswv|Gold]] || E0 E1 E2 E3 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
 
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| [[Cores/Decimal8/Encoding#607|Decimal8]] || E0 E1 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
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| [[Cores/Decimal8/Encoding#mulswv|Decimal8]] || E0 E1 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
 
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| [[Cores/Decimal16/Encoding#607|Decimal16]] || E0 E1 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
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| [[Cores/Decimal16/Encoding#mulswv|Decimal16]] || E0 E1 || bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6  
 
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

multiplication

mulswv(s x, s y) → s r0, s r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6
Copper E0 bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6
Silver E0 E1 bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6
Gold E0 E1 E2 E3 bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6
Decimal8 E0 E1 bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6
Decimal16 E0 E1 bv,bv:hv,hv=3,3 hv,hv:wv,wv=4,4 wv,wv:dv,dv=5,5 dv,dv:qv,qv=6,6


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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