Difference between revisions of "Instruction Set/exuArgs"

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(Created page with "{{DISPLAYTITLE:exuArgs}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bloc...")
 
Line 14:Line 14:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#64|Tin]] || E0 E1 || 0
+
| [[Cores/Tin/Encoding#exuArgs|Tin]] || E0 E1 || 0
 
|-
 
|-
−
| [[Cores/Copper/Encoding#64|Copper]] || E0 E1 || 0
+
| [[Cores/Copper/Encoding#exuArgs|Copper]] || E0 E1 || 0
 
|-
 
|-
−
| [[Cores/Silver/Encoding#64|Silver]] || E0 E1 E2 E3 || 0
+
| [[Cores/Silver/Encoding#exuArgs|Silver]] || E0 E1 E2 E3 || 0
 
|-
 
|-
−
| [[Cores/Gold/Encoding#64|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 0
+
| [[Cores/Gold/Encoding#exuArgs|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 0
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#64|Decimal8]] || E0 E1 E2 E3 || 0
+
| [[Cores/Decimal8/Encoding#exuArgs|Decimal8]] || E0 E1 E2 E3 || 0
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#64|Decimal16]] || E0 E1 E2 E3 || 0
+
| [[Cores/Decimal16/Encoding#exuArgs|Decimal16]] || E0 E1 E2 E3 || 0
 
|}
 
|}
  
Line 36:Line 36:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#65|Tin]] || E0 E1 || 0
+
| [[Cores/Tin/Encoding#exuArgs|Tin]] || E0 E1 || 0
 
|-
 
|-
−
| [[Cores/Copper/Encoding#65|Copper]] || E0 E1 || 0
+
| [[Cores/Copper/Encoding#exuArgs|Copper]] || E0 E1 || 0
 
|-
 
|-
−
| [[Cores/Silver/Encoding#65|Silver]] || E0 E1 E2 E3 || 0
+
| [[Cores/Silver/Encoding#exuArgs|Silver]] || E0 E1 E2 E3 || 0
 
|-
 
|-
−
| [[Cores/Gold/Encoding#65|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 0
+
| [[Cores/Gold/Encoding#exuArgs|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 0
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#65|Decimal8]] || E0 E1 E2 E3 || 0
+
| [[Cores/Decimal8/Encoding#exuArgs|Decimal8]] || E0 E1 E2 E3 || 0
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#65|Decimal16]] || E0 E1 E2 E3 || 0
+
| [[Cores/Decimal16/Encoding#exuArgs|Decimal16]] || E0 E1 E2 E3 || 0
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  exu stream  exu block  compute phase   operation  

native on: all

additional slot for ganged exu operation

exuArgs(op arg)

operands: like Inv :


Core In Slots Latencies
Tin E0 E1 0
Copper E0 E1 0
Silver E0 E1 E2 E3 0
Gold E0 E1 E2 E3 E4 E5 E6 E7 0
Decimal8 E0 E1 E2 E3 0
Decimal16 E0 E1 E2 E3 0

exuArgs(op arg0, op arg1)

operands: like Inv :


Core In Slots Latencies
Tin E0 E1 0
Copper E0 E1 0
Silver E0 E1 E2 E3 0
Gold E0 E1 E2 E3 E4 E5 E6 E7 0
Decimal8 E0 E1 E2 E3 0
Decimal16 E0 E1 E2 E3 0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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