Difference between revisions of "Instruction Set/br"

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(Created page with "{{DISPLAYTITLE:br}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream  flow block...")
 
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</div>
 
</div>
  
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branch
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Conditionless branch.
 +
There must always be exactly one conditionless branch or return operation in every [[EBB]], and always in last position. There can be several conditionless branches in an EBB and even in the same operation, which are all processes in parallel, but the first successful in the lowest slot wins.
 +
 
 +
The targets in branches, whether literal or from a belt operand, are always relative to the  [[Registers|EBB entry point]]. The optional delay serves to synchronize with operations that need to finish before control is transferred to the next EBB.
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<b>related operations:</b> [[Instruction_Set/brtr|brtr]], [[Instruction_Set/brfl|brfl]]
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----
 
----
 
<code style="font-size:130%"><b style="color:#050">br</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from opsWindow">target</span>)</code>
 
<code style="font-size:130%"><b style="color:#050">br</b>(<span style="color:#009">[[Domains#p|p]]</span> <span title="belt operand from opsWindow">target</span>)</code>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#220|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#br|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#220|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#br|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#220|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#br|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#220|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#br|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#220|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#br|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#220|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#br|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#217|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#br|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#217|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#br|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#217|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#br|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#217|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#br|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#217|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#br|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#217|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#br|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#218|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#br|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#218|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#br|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#218|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#br|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#218|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#br|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#218|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#br|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#218|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#br|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#219|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#br|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#219|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#br|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#219|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#br|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#219|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#br|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#219|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#br|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#219|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#br|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  flow stream  flow block  transfer phase   operation  

native on: all

Conditionless branch. There must always be exactly one conditionless branch or return operation in every EBB, and always in last position. There can be several conditionless branches in an EBB and even in the same operation, which are all processes in parallel, but the first successful in the lowest slot wins.

The targets in branches, whether literal or from a belt operand, are always relative to the EBB entry point. The optional delay serves to synchronize with operations that need to finish before control is transferred to the next EBB.

related operations: brtr, brfl


br(p target)

operands: like Inv :


Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

br(p target, lit delay)

operands: like Inv :


Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

br(lbl target)

operands: like Inv :


Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

br(lbl target, lit delay)

operands: like Inv :


Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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