Difference between revisions of "Instruction Set/addf"
From Mill Computing Wiki
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#addf|Silver]] || E0 E1 || w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#addf|Gold]] || E0 E1 E2 E3 || w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5 |
|} | |} | ||
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| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 02:38, 16 December 2014
realizing exu stream exu block compute phase operation in the binary floating point value domain that produces condition codes
Floating point add in current rounding mode.
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5 |
| Gold | E0 E1 E2 E3 | w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
