Difference between revisions of "Instruction Set/narrowffz"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:narrowffz}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu bl...") | |||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#narrowffz|Silver]] || E0 E1 || w:h=3 d:w=4 q:d=5 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#narrowffz|Gold]] || E0 E1 E2 E3 || w:h=3 d:w=4 q:d=5 |
|} | |} | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#narrowffz|Silver]] || E0 E1 || wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#narrowffz|Gold]] || E0 E1 E2 E3 || wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5 |
|} | |} | ||
| + | |||
| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 02:38, 16 December 2014
narrow scalar to half width
operands: like Narrowf [ff:½f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w:h=3 d:w=4 q:d=5 |
| Gold | E0 E1 E2 E3 | w:h=3 d:w=4 q:d=5 |
operands: like Narrowvf [FF:½F]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5 |
| Gold | E0 E1 E2 E3 | wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
