Difference between revisions of "Instruction Set/mulsw"
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(Created page with "{{DISPLAYTITLE:mulsw}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream [[Decode|exu block]...") | |||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#mulsw|Tin]] || E0 || b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#mulsw|Copper]] || E0 || b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#mulsw|Silver]] || E0 E1 || b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#mulsw|Gold]] || E0 E1 E2 E3 || b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#mulsw|Decimal8]] || E0 E1 || b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#mulsw|Decimal16]] || E0 E1 || b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
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+ | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Revision as of 02:38, 16 December 2014
realizing exu stream exu block compute phase operation in the signed integer value domain using widening overflow behavior that produces condition codes
native on: all
multiplication
operands: like Widen xx:2x
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
Copper | E0 | b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
Silver | E0 E1 | b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
Gold | E0 E1 E2 E3 | b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
Decimal8 | E0 E1 | b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
Decimal16 | E0 E1 | b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable