Difference between revisions of "Instruction Set/con"
From Mill Computing Wiki
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#con|Tin]] || F0 F1 || 0 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#con|Copper]] || F0 F1 || 0 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#con|Silver]] || F0 F1 F2 F3 || 0 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#con|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 0 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#con|Decimal8]] || F0 F1 F2 F3 || 0 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#con|Decimal16]] || F0 F1 F2 F3 || 0 |
|} | |} | ||
| + | |||
| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 02:37, 16 December 2014
Drop an immediate constant on the belt.
The con operation retires in the reader phase despite it using the extension and manifest encoding blocks for the value. This is possible because these bitpatterns are not interpreted at all but directly placed into the belt. Only scalar values are possible, and the width is determined from the head.
related operations: rd
operands: like IdentityNoSIMD xx:x
encoding:
con(off v, width w)
,
con(off v, width w, lit v)
,
con(off v, width w, lit v, lit v)
,
con(off v, width w, lit v, lit v, lit v)
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 F1 | 0 |
| Copper | F0 F1 | 0 |
| Silver | F0 F1 F2 F3 | 0 |
| Gold | F0 F1 F2 F3 F4 F5 F6 F7 | 0 |
| Decimal8 | F0 F1 F2 F3 | 0 |
| Decimal16 | F0 F1 F2 F3 | 0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
