Difference between revisions of "Instruction Set/f2sdxfz"
From Mill Computing Wiki
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
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| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#f2sdxfz|Decimal8]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#f2sdxfz|Decimal16]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
|} | |} | ||
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| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 02:37, 16 December 2014
realizing exu stream exu block compute phase operation in the decimal floating point value domain using excepting overflow behavior that produces condition codes
Inexactly convert a decimal floating point value to a signed integer, rounding away from zero and producing NaRs on overflow.
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
