Difference between revisions of "Instruction Set/addsw"
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| − | addition | + | Widening signed integer addition. |
| + | When a result value overflows, it is widened. | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">addsw</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#s|s]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">addsw</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#s|s]] r<sub>0</sub></code> | ||
Revision as of 10:16, 12 November 2014
realizing exu stream exu block compute phase operation in the signed integer value domain using widening overflow behavior that produces condition codes
native on: all
Widening signed integer addition. When a result value overflows, it is widened.
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Copper | E0 E1 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Silver | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal8 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal16 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Copper | E0 E1 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Silver | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal8 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
| Decimal16 | E0 E1 E2 E3 | b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2 |
