Difference between revisions of "Instruction Set/widendv"

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(Created page with "{{DISPLAYTITLE:widendv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bloc...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Decimal8/Encoding#901|Decimal8]] || E0 E1 || 2 2
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| [[Cores/Decimal8/Encoding#widendv|Decimal8]] || E0 E1 || 2 2
 
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|-
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| [[Cores/Decimal16/Encoding#901|Decimal16]] || E0 E1 || 2 2
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| [[Cores/Decimal16/Encoding#widendv|Decimal16]] || E0 E1 || 2 2
 
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the decimal floating point value domain  

native on: Decimal8 Decimal16

widen to double width

widendv(d v) → d r0, d r1

operands: like Widenvd DD:2D2D


Core In Slots Latencies
Decimal8 E0 E1 2 2
Decimal16 E0 E1 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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