Difference between revisions of "Instruction Set/stored"

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(Created page with "{{DISPLAYTITLE:stored}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow blo...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#830|Decimal8]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal8/Encoding#stored|Decimal8]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#830|Decimal16]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal16/Encoding#stored|Decimal16]] || F0 F1 F2 F3 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#834|Decimal8]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal8/Encoding#stored|Decimal8]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#834|Decimal16]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal16/Encoding#stored|Decimal16]] || F0 F1 F2 F3 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#832|Decimal8]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal8/Encoding#stored|Decimal8]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#832|Decimal16]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal16/Encoding#stored|Decimal16]] || F0 F1 F2 F3 || 1
 
|}
 
|}
  
Line 58:Line 58:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#831|Decimal8]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal8/Encoding#stored|Decimal8]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#831|Decimal16]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal16/Encoding#stored|Decimal16]] || F0 F1 F2 F3 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#833|Decimal8]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal8/Encoding#stored|Decimal8]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#833|Decimal16]] || F0 F1 F2 F3 || 1
+
| [[Cores/Decimal16/Encoding#stored|Decimal16]] || F0 F1 F2 F3 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  flow stream  flow block  writer phase   operation   in the decimal floating point value domain  

native on: Decimal8 Decimal16

store to memory

stored(base b, off o, s i, scale s, d v)

operands: like NoResult [xx]:


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 1
Decimal16 F0 F1 F2 F3 1

stored(base b, off o, d v)

operands: like NoResult [xx]:


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 1
Decimal16 F0 F1 F2 F3 1

stored(p b, off o, s i, scale s, d v)

operands: like NoResult [xx]:


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 1
Decimal16 F0 F1 F2 F3 1

stored(p b, off o, d v)

operands: like NoResult [xx]:


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 1
Decimal16 F0 F1 F2 F3 1

stored(p b, d v, memAttr m)

operands: like NoResult [xx]:


Core In Slots Latencies
Decimal8 F0 F1 F2 F3 1
Decimal16 F0 F1 F2 F3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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