Difference between revisions of "Instruction Set/call1"

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(Created page with "{{DISPLAYTITLE:call1}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow bloc...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Tin/Encoding#940|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#call1|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#940|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#call1|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#940|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#call1|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#940|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#call1|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#940|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#call1|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#940|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#call1|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#941|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#call1|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#941|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#call1|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#941|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#call1|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#941|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#call1|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#941|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#call1|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#941|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#call1|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  flow stream  flow block  call phase   operation  

native on: all

function call

call1(p target, args args) → op r

operands: like Inv :


encoding: call1(op q, off target, count argc) , call1(op q, off target, count argc, lit argv) , call1(op q, off target, count argc, lit argv, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

call1(lbl target, args args) → op r

operands: like Inv :


encoding: call1(off target, count argc) , call1(off target, count argc, lit argv) , call1(off target, count argc, lit argv, lit argv) , call1(off target, count argc, lit argv, lit argv, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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