Difference between revisions of "Instruction Set/rotater"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:rotater}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bloc...")
 
Line 14:Line 14:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#749|Tin]] || E0 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Tin/Encoding#rotater|Tin]] || E0 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|-
 
|-
| [[Cores/Copper/Encoding#749|Copper]] || E0 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Copper/Encoding#rotater|Copper]] || E0 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|-
 
|-
| [[Cores/Silver/Encoding#749|Silver]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Silver/Encoding#rotater|Silver]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|-
 
|-
| [[Cores/Gold/Encoding#749|Gold]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Gold/Encoding#rotater|Gold]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|-
 
|-
| [[Cores/Decimal8/Encoding#749|Decimal8]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Decimal8/Encoding#rotater|Decimal8]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|-
 
|-
| [[Cores/Decimal16/Encoding#749|Decimal16]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Decimal16/Encoding#rotater|Decimal16]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|}
 
|}
  
Line 36:Line 36:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#748|Tin]] || E0 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Tin/Encoding#rotater|Tin]] || E0 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|-
 
|-
| [[Cores/Copper/Encoding#748|Copper]] || E0 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Copper/Encoding#rotater|Copper]] || E0 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|-
 
|-
| [[Cores/Silver/Encoding#748|Silver]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Silver/Encoding#rotater|Silver]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|-
 
|-
| [[Cores/Gold/Encoding#748|Gold]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Gold/Encoding#rotater|Gold]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|-
 
|-
| [[Cores/Decimal8/Encoding#748|Decimal8]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Decimal8/Encoding#rotater|Decimal8]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|-
 
|-
| [[Cores/Decimal16/Encoding#748|Decimal16]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
+
| [[Cores/Decimal16/Encoding#rotater|Decimal16]] || E0 E1 || b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2  
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain   that produces condition codes

native on: all

bitwise rotate


rotater(op x, bit bits) → op r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Copper E0 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Silver E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Gold E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Decimal8 E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Decimal16 E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2

rotater(op x, u bits) → op r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Copper E0 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Silver E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Gold E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Decimal8 E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2
Decimal16 E0 E1 b,b:b=1 b,h:b=1 b,w:b=1 b,d:b=1 b,q:b=1 bv,bv:bv=1 h,b:h=1 h,h:h=1 h,w:h=1 h,d:h=1 h,q:h=1 hv,hv:hv=1 w,b:w=1 w,h:w=1 w,w:w=1 w,d:w=1 w,q:w=1 wv,wv:wv=1 d,b:d=2 d,h:d=2 d,w:d=2 d,d:d=2 d,q:d=2 dv,dv:dv=2 q,b:q=2 q,h:q=2 q,w:q=2 q,d:q=2 q,q:q=2 qv,qv:qv=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable