Difference between revisions of "Instruction Set/flip"

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(Created page with "{{DISPLAYTITLE:flip}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream  exu block...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#446|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#flip|Tin]] || E0 || 1
 
|-
 
|-
| [[Cores/Copper/Encoding#446|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#flip|Copper]] || E0 E1 || 1
 
|-
 
|-
| [[Cores/Silver/Encoding#446|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#flip|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
| [[Cores/Gold/Encoding#446|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#flip|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
| [[Cores/Decimal8/Encoding#446|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#flip|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
| [[Cores/Decimal16/Encoding#446|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#flip|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
  
Line 37:Line 37:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#448|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#flip|Tin]] || E0 || 1
 
|-
 
|-
| [[Cores/Copper/Encoding#448|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#flip|Copper]] || E0 E1 || 1
 
|-
 
|-
| [[Cores/Silver/Encoding#448|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#flip|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
| [[Cores/Gold/Encoding#448|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#flip|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
| [[Cores/Decimal8/Encoding#448|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#flip|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
| [[Cores/Decimal16/Encoding#448|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#flip|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
  
Line 59:Line 59:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#447|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#flip|Tin]] || E0 || 1
 
|-
 
|-
| [[Cores/Copper/Encoding#447|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#flip|Copper]] || E0 E1 || 1
 
|-
 
|-
| [[Cores/Silver/Encoding#447|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#flip|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
| [[Cores/Gold/Encoding#447|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#flip|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
| [[Cores/Decimal8/Encoding#447|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#flip|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
| [[Cores/Decimal16/Encoding#447|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#flip|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

aliases: flips flipu
native on: all

bit complement


flip(op x) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1

flip(op x, bit bit) → op r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1

flip(op x, n bit) → op r0

operands: like Shift [xi:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable