Difference between revisions of "Instruction Set/widenfv"

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(Created page with "{{DISPLAYTITLE:widenfv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bloc...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Silver/Encoding#903|Silver]] || E0 E1 || 2 2
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| [[Cores/Silver/Encoding#widenfv|Silver]] || E0 E1 || 2 2
 
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| [[Cores/Gold/Encoding#903|Gold]] || E0 E1 E2 E3 || 2 2
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| [[Cores/Gold/Encoding#widenfv|Gold]] || E0 E1 E2 E3 || 2 2
 
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:39, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the binary floating point value domain  

native on: Silver Gold

widen to double width

widenfv(f v) → f r0, f r1

operands: like Widenvf FF:2F2F


Core In Slots Latencies
Silver E0 E1 2 2
Gold E0 E1 E2 E3 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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