Difference between revisions of "Instruction Set/mulufwe"
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
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| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#mulufwe|Tin]] || E0 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#mulufwe|Copper]] || E0 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#mulufwe|Silver]] || E0 E1 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#mulufwe|Gold]] || E0 E1 E2 E3 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#mulufwe|Decimal8]] || E0 E1 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#mulufwe|Decimal16]] || E0 E1 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
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| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 02:38, 16 December 2014
realizing exu stream exu block compute phase operation in the unsigned fixed point value domain using widening overflow behavior that produces condition codes
native on: all
multiplication
mulufwe(uf x, uf y, bit dot) → uf r0
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Copper | E0 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Silver | E0 E1 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Gold | E0 E1 E2 E3 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Decimal8 | E0 E1 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
| Decimal16 | E0 E1 | b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
