Difference between revisions of "Instruction Set/rd"

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(Created page with "{{DISPLAYTITLE:rd}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|reader block]...")
 
Line 14:Line 14:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#715|Tin]] || R0 R1 || 0
+
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 0
 
|-
 
|-
−
| [[Cores/Copper/Encoding#715|Copper]] || R0 R1 || 0
+
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 0
 
|-
 
|-
−
| [[Cores/Silver/Encoding#715|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 R4 R5 || 0
 
|-
 
|-
−
| [[Cores/Gold/Encoding#715|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#715|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Decimal8/Encoding#rd|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#715|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Decimal16/Encoding#rd|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
 
|}
 
|}
  
Line 36:Line 36:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#714|Tin]] || R0 R1 || 0
+
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 0
 
|-
 
|-
−
| [[Cores/Copper/Encoding#714|Copper]] || R0 R1 || 0
+
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 0
 
|-
 
|-
−
| [[Cores/Silver/Encoding#714|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 R4 R5 || 0
 
|-
 
|-
−
| [[Cores/Gold/Encoding#714|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#714|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Decimal8/Encoding#rd|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#714|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Decimal16/Encoding#rd|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
 
|}
 
|}
  
Line 58:Line 58:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#712|Tin]] || R0 R1 || 0
+
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 0
 
|-
 
|-
−
| [[Cores/Copper/Encoding#712|Copper]] || R0 R1 || 0
+
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 0
 
|-
 
|-
−
| [[Cores/Silver/Encoding#712|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 R4 R5 || 0
 
|-
 
|-
−
| [[Cores/Gold/Encoding#712|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#712|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Decimal8/Encoding#rd|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#712|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Decimal16/Encoding#rd|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
 
|}
 
|}
  
Line 80:Line 80:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#713|Tin]] || R0 R1 || 0
+
| [[Cores/Tin/Encoding#rd|Tin]] || R0 R1 || 0
 
|-
 
|-
−
| [[Cores/Copper/Encoding#713|Copper]] || R0 R1 || 0
+
| [[Cores/Copper/Encoding#rd|Copper]] || R0 R1 || 0
 
|-
 
|-
−
| [[Cores/Silver/Encoding#713|Silver]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Silver/Encoding#rd|Silver]] || R0 R1 R2 R3 R4 R5 || 0
 
|-
 
|-
−
| [[Cores/Gold/Encoding#713|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
+
| [[Cores/Gold/Encoding#rd|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 0
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#713|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Decimal8/Encoding#rd|Decimal8]] || R0 R1 R2 R3 R4 R5 || 0
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#713|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
+
| [[Cores/Decimal16/Encoding#rd|Decimal16]] || R0 R1 R2 R3 R4 R5 || 0
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  reader block  reader phase   operation   in the logical value domain  

native on: all

hardware reader

rd(const src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 0
Copper R0 R1 0
Silver R0 R1 R2 R3 R4 R5 0
Gold R0 R1 R2 R3 R4 R5 R6 R7 0
Decimal8 R0 R1 R2 R3 R4 R5 0
Decimal16 R0 R1 R2 R3 R4 R5 0

rd(scratch src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 0
Copper R0 R1 0
Silver R0 R1 R2 R3 R4 R5 0
Gold R0 R1 R2 R3 R4 R5 R6 R7 0
Decimal8 R0 R1 R2 R3 R4 R5 0
Decimal16 R0 R1 R2 R3 R4 R5 0

rd(reg src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 0
Copper R0 R1 0
Silver R0 R1 R2 R3 R4 R5 0
Gold R0 R1 R2 R3 R4 R5 R6 R7 0
Decimal8 R0 R1 R2 R3 R4 R5 0
Decimal16 R0 R1 R2 R3 R4 R5 0

rd(stream src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 0
Copper R0 R1 0
Silver R0 R1 R2 R3 R4 R5 0
Gold R0 R1 R2 R3 R4 R5 R6 R7 0
Decimal8 R0 R1 R2 R3 R4 R5 0
Decimal16 R0 R1 R2 R3 R4 R5 0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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