Difference between revisions of "Instruction Set/f2sdfz"
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| − | convert | + | Inexactly convert a decimal floating point value to a signed integer, rounding away from zero and normal modulo overflow. |
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<code style="font-size:130%"><b style="color:#050">f2sdfz</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#d|d]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">f2sdfz</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#d|d]] r<sub>0</sub></code> | ||
Revision as of 10:18, 12 November 2014
realizing exu stream exu block compute phase operation in the decimal floating point value domain using modulo overflow behavior that produces condition codes
Inexactly convert a decimal floating point value to a signed integer, rounding away from zero and normal modulo overflow.
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
