Difference between revisions of "Instruction Set/widenv"

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(Created page with "{{DISPLAYTITLE:widenv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu block...")
 
Line 15:Line 15:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#911|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#widenv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#911|Copper]] || E0 E1 || 2 2
+
| [[Cores/Copper/Encoding#widenv|Copper]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#911|Silver]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Silver/Encoding#widenv|Silver]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#911|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
+
| [[Cores/Gold/Encoding#widenv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#911|Decimal8]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal8/Encoding#widenv|Decimal8]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#911|Decimal16]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal16/Encoding#widenv|Decimal16]] || E0 E1 E2 E3 || 2 2
 
|}
 
|}
  
Line 37:Line 37:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#910|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#widenv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#910|Copper]] || E0 E1 || 2 2
+
| [[Cores/Copper/Encoding#widenv|Copper]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#910|Silver]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Silver/Encoding#widenv|Silver]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#910|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
+
| [[Cores/Gold/Encoding#widenv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#910|Decimal8]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal8/Encoding#widenv|Decimal8]] || E0 E1 E2 E3 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#910|Decimal16]] || E0 E1 E2 E3 || 2 2
+
| [[Cores/Decimal16/Encoding#widenv|Decimal16]] || E0 E1 E2 E3 || 2 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

aliases: widenuv
native on: all

widen to double width

widenv(op v) → op r0, op r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2

widenv(op v1, op v2) → op r0, op r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 E1 2 2
Silver E0 E1 E2 E3 2 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2 2
Decimal8 E0 E1 E2 E3 2 2
Decimal16 E0 E1 E2 E3 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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