Difference between revisions of "Instruction Set/f2uedsp"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:f2uedsp}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu bloc...") | |||
| Line 4: | Line 4: | ||
</div> | </div> | ||
| − | convert | + | Exactly convert a decimal floating point value to a unsigned integer, rounding toward positive infinity and producing saturating result values. |
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">f2uedsp</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#d|d]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">f2uedsp</b>(<span style="color:#009">[[Domains#d|d]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#d|d]] r<sub>0</sub></code> | ||
Revision as of 10:18, 12 November 2014
realizing exu stream exu block compute phase operation in the decimal floating point value domain using saturating overflow behavior that produces condition codes
Exactly convert a decimal floating point value to a unsigned integer, rounding toward positive infinity and producing saturating result values.
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
