Difference between revisions of "Instruction Set/narrowux"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:narrowux}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu blo...")
 
Line 14:Line 14:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#671|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#narrowux|Tin]] || E0 || 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#671|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#narrowux|Copper]] || E0 E1 || 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#671|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#narrowux|Silver]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#671|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#narrowux|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#671|Decimal8]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal8/Encoding#narrowux|Decimal8]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#671|Decimal16]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal16/Encoding#narrowux|Decimal16]] || E0 E1 E2 E3 || 2
 
|}
 
|}
  
Line 36:Line 36:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#672|Tin]] || E0 || 2
+
| [[Cores/Tin/Encoding#narrowux|Tin]] || E0 || 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#672|Copper]] || E0 E1 || 2
+
| [[Cores/Copper/Encoding#narrowux|Copper]] || E0 E1 || 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#672|Silver]] || E0 E1 E2 E3 || 2
+
| [[Cores/Silver/Encoding#narrowux|Silver]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#672|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
+
| [[Cores/Gold/Encoding#narrowux|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#672|Decimal8]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal8/Encoding#narrowux|Decimal8]] || E0 E1 E2 E3 || 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#672|Decimal16]] || E0 E1 E2 E3 || 2
+
| [[Cores/Decimal16/Encoding#narrowux|Decimal16]] || E0 E1 E2 E3 || 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   using excepting overflow behavior  

native on: all

narrow scalar to half width

narrowux(u v) → u r0

operands: like Narrow [xx:½x]


Core In Slots Latencies
Tin E0 2
Copper E0 E1 2
Silver E0 E1 E2 E3 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2
Decimal8 E0 E1 E2 E3 2
Decimal16 E0 E1 E2 E3 2

narrowux(u v1, u v2) → u r0

operands: like Narrowv [XX:½x]


Core In Slots Latencies
Tin E0 2
Copper E0 E1 2
Silver E0 E1 E2 E3 2
Gold E0 E1 E2 E3 E4 E5 E6 E7 2
Decimal8 E0 E1 E2 E3 2
Decimal16 E0 E1 E2 E3 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/narrowux&oldid=1768"