Difference between revisions of "Instruction Set/shiftluwv"

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(Created page with "{{DISPLAYTITLE:shiftluwv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bl...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#800|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#shiftluwv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#800|Copper]] || E0 || 2 2
+
| [[Cores/Copper/Encoding#shiftluwv|Copper]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#800|Silver]] || E0 E1 || 2 2
+
| [[Cores/Silver/Encoding#shiftluwv|Silver]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#800|Gold]] || E0 E1 || 2 2
+
| [[Cores/Gold/Encoding#shiftluwv|Gold]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#800|Decimal8]] || E0 E1 || 2 2
+
| [[Cores/Decimal8/Encoding#shiftluwv|Decimal8]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#800|Decimal16]] || E0 E1 || 2 2
+
| [[Cores/Decimal16/Encoding#shiftluwv|Decimal16]] || E0 E1 || 2 2
 
|}
 
|}
  
Line 36:Line 36:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#799|Tin]] || E0 || 2 2
+
| [[Cores/Tin/Encoding#shiftluwv|Tin]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Copper/Encoding#799|Copper]] || E0 || 2 2
+
| [[Cores/Copper/Encoding#shiftluwv|Copper]] || E0 || 2 2
 
|-
 
|-
−
| [[Cores/Silver/Encoding#799|Silver]] || E0 E1 || 2 2
+
| [[Cores/Silver/Encoding#shiftluwv|Silver]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Gold/Encoding#799|Gold]] || E0 E1 || 2 2
+
| [[Cores/Gold/Encoding#shiftluwv|Gold]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#799|Decimal8]] || E0 E1 || 2 2
+
| [[Cores/Decimal8/Encoding#shiftluwv|Decimal8]] || E0 E1 || 2 2
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#799|Decimal16]] || E0 E1 || 2 2
+
| [[Cores/Decimal16/Encoding#shiftluwv|Decimal16]] || E0 E1 || 2 2
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   using widening overflow behavior   that produces condition codes

native on: all

bitwise shift

shiftluwv(u x, bit bits) → u r0, u r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 2 2
Silver E0 E1 2 2
Gold E0 E1 2 2
Decimal8 E0 E1 2 2
Decimal16 E0 E1 2 2

shiftluwv(u x, n bits) → u r0, u r1

operands: like Widenv XX:2X2X


Core In Slots Latencies
Tin E0 2 2
Copper E0 2 2
Silver E0 E1 2 2
Gold E0 E1 2 2
Decimal8 E0 E1 2 2
Decimal16 E0 E1 2 2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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