Difference between revisions of "Instruction Set/innertr1"

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(Created page with "{{DISPLAYTITLE:innertr1}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow b...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Tin/Encoding#1015|Tin]] || F0 || 1
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| [[Cores/Tin/Encoding#innertr1|Tin]] || F0 || 1
 
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|-
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| [[Cores/Copper/Encoding#1015|Copper]] || F0 F1 || 1
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| [[Cores/Copper/Encoding#innertr1|Copper]] || F0 F1 || 1
 
|-
 
|-
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| [[Cores/Silver/Encoding#1015|Silver]] || F0 F1 F2 || 1
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| [[Cores/Silver/Encoding#innertr1|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
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| [[Cores/Gold/Encoding#1015|Gold]] || F0 F1 F2 F3 || 1
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| [[Cores/Gold/Encoding#innertr1|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
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| [[Cores/Decimal8/Encoding#1015|Decimal8]] || F0 F1 F2 || 1
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| [[Cores/Decimal8/Encoding#innertr1|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1015|Decimal16]] || F0 F1 F2 || 1
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| [[Cores/Decimal16/Encoding#innertr1|Decimal16]] || F0 F1 F2 || 1
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#1016|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#innertr1|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#1016|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#innertr1|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#1016|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#innertr1|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#1016|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#innertr1|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#1016|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#innertr1|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#1016|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#innertr1|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  flow stream  flow block  call phase   operation  

native on: all

enter a loop

innertr1(op q, p target, args args) → op r

operands: like Inv :


encoding: innertr1(op q, p target, off argv, count argc) , innertr1(op q, p target, off argv, count argc, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

innertr1(op q, lbl target, args args) → op r

operands: like Inv :


encoding: innertr1(op q, off target, count argc) , innertr1(op q, off target, count argc, lit argv) , innertr1(op q, off target, count argc, lit argv, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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