Difference between revisions of "Instruction Set/f2sfp"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:f2sfp}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream [[Decode|exu block]...") | |||
| Line 4: | Line 4: | ||
</div> | </div> | ||
| − | convert | + | Inexactly convert a binary floating point value to a signed integer, rounding toward positive infinity and normal modulo overflow. |
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">f2sfp</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#f|f]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">f2sfp</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#f|f]] r<sub>0</sub></code> | ||
Revision as of 10:17, 12 November 2014
realizing exu stream exu block compute phase operation in the binary floating point value domain using modulo overflow behavior that produces condition codes
Inexactly convert a binary floating point value to a signed integer, rounding toward positive infinity and normal modulo overflow.
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Gold | E0 E1 E2 E3 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
