Difference between revisions of "Instruction Set/fmafz"

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(Created page with "{{DISPLAYTITLE:fmafz}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|exu block]...")
 
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| [[Cores/Silver/Encoding#986|Silver]] || E0 E1 || w,w:w=6 wv,wv:wv=6 d,d:d=7 dv,dv:dv=7 q,q:q=8 qv,qv:qv=8  
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| [[Cores/Silver/Encoding#fmafz|Silver]] || E0 E1 || w,w:w=6 wv,wv:wv=6 d,d:d=7 dv,dv:dv=7 q,q:q=8 qv,qv:qv=8  
 
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| [[Cores/Gold/Encoding#986|Gold]] || E0 E1 E2 E3 || w,w:w=6 wv,wv:wv=6 d,d:d=7 dv,dv:dv=7 q,q:q=8 qv,qv:qv=8  
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| [[Cores/Gold/Encoding#fmafz|Gold]] || E0 E1 E2 E3 || w,w:w=6 wv,wv:wv=6 d,d:d=7 dv,dv:dv=7 q,q:q=8 qv,qv:qv=8  
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Silver/Encoding#987|Silver]] || E0 || w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=7,7 dv,dv:dv,dv=7,7 q,q:q,q=8,8 qv,qv:qv,qv=8,8  
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| [[Cores/Silver/Encoding#fmafz|Silver]] || E0 || w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=7,7 dv,dv:dv,dv=7,7 q,q:q,q=8,8 qv,qv:qv,qv=8,8  
 
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| [[Cores/Gold/Encoding#987|Gold]] || E0 E2 || w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=7,7 dv,dv:dv,dv=7,7 q,q:q,q=8,8 qv,qv:qv,qv=8,8  
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| [[Cores/Gold/Encoding#fmafz|Gold]] || E0 E2 || w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=7,7 dv,dv:dv,dv=7,7 q,q:q,q=8,8 qv,qv:qv,qv=8,8  
 
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the binary floating point value domain  

native on: Silver Gold

fused multiply-add or -add/subtract

fmafz(f x, f y, f z) → f r0

operands: like Addf [ff:f]


encoding: fmafz(f x) , exuArgs(op arg0, op arg1)

Core In Slots Latencies
Silver E0 E1 w,w:w=6 wv,wv:wv=6 d,d:d=7 dv,dv:dv=7 q,q:q=8 qv,qv:qv=8
Gold E0 E1 E2 E3 w,w:w=6 wv,wv:wv=6 d,d:d=7 dv,dv:dv=7 q,q:q=8 qv,qv:qv=8

fmafz(f x, f y, f z, f w) → f r0, f r1

operands: like Fmasf [ff:f]


encoding: fmafz(f x, f y) , exuArgs(op arg0, op arg1)

Core In Slots Latencies
Silver E0 w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=7,7 dv,dv:dv,dv=7,7 q,q:q,q=8,8 qv,qv:qv,qv=8,8
Gold E0 E2 w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=7,7 dv,dv:dv,dv=7,7 q,q:q,q=8,8 qv,qv:qv,qv=8,8


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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