Difference between revisions of "Instruction Set/rotate"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:rotate}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|reader bl...") | |||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#rotate|Tin]] || R0 R1 || 1 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#rotate|Copper]] || R0 R1 || 1 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#rotate|Silver]] || R0 R1 R2 R3 R4 R5 || 1 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#rotate|Gold]] || R0 R1 R2 R3 R4 R5 R6 R7 || 1 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#rotate|Decimal8]] || R0 R1 R2 R3 R4 R5 || 1 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#rotate|Decimal16]] || R0 R1 R2 R3 R4 R5 || 1 |
|} | |} | ||
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| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 02:37, 16 December 2014
realizing exu stream reader block compute phase operation in the logical value domain
native on: all
bitwise rotate
rotate(scratch id)
operands: like NoArgs :[x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | R0 R1 | 1 |
| Copper | R0 R1 | 1 |
| Silver | R0 R1 R2 R3 R4 R5 | 1 |
| Gold | R0 R1 R2 R3 R4 R5 R6 R7 | 1 |
| Decimal8 | R0 R1 R2 R3 R4 R5 | 1 |
| Decimal16 | R0 R1 R2 R3 R4 R5 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
