Difference between revisions of "Instruction Set/innertrn"
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(Created page with "{{DISPLAYTITLE:innertrn}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing flow stream Decode|flow b...") | |||
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|flow stream]] [[Decode|flow block]] [[Phasing|call phase]] operation <br /> | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|flow stream]] [[Decode|flow block]] [[Phasing|call phase]] operation <br /> | ||
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'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
Revision as of 13:56, 26 October 2014
enter a loop
innertrn(op q, lit n, p target, args args) → ops r0 ...rn
operands: like Inv :
encoding:
innertrn(op q, lit n, p target, off argc, count args)
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 F1 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 F1 F2 F3 | 1 |
| Decimal8 | F0 F1 F2 | 1 |
| Decimal16 | F0 F1 F2 | 1 |
innertrn(op q, lit n, lbl target, args args) → ops r0 ...rn
operands: like Inv :
encoding:
innertrn(op q, lit n, off target, count argc)
,
innertrn(op q, lit n, off target, count argc, lit argv)
| Core | In Slots | Latencies |
|---|---|---|
| Tin | F0 | 1 |
| Copper | F0 F1 | 1 |
| Silver | F0 F1 F2 | 1 |
| Gold | F0 F1 F2 F3 | 1 |
| Decimal8 | F0 F1 F2 | 1 |
| Decimal16 | F0 F1 F2 | 1 |
