Difference between revisions of "Instruction Set/storef"

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(Created page with "{{DISPLAYTITLE:storef}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow blo...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#838|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#storef|Silver]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#838|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#storef|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#839|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#storef|Silver]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#839|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#storef|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#836|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#storef|Silver]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#836|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#storef|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#837|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#storef|Silver]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#837|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#storef|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Silver/Encoding#835|Silver]] || F0 F1 F2 F3 || 1
+
| [[Cores/Silver/Encoding#storef|Silver]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#835|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
+
| [[Cores/Gold/Encoding#storef|Gold]] || F0 F1 F2 F3 F4 F5 F6 F7 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  flow stream  flow block  writer phase   operation   in the binary floating point value domain  

native on: Silver Gold

store to memory

storef(base b, off o, s i, scale s, f v)

operands: like NoResult [xx]:


Core In Slots Latencies
Silver F0 F1 F2 F3 1
Gold F0 F1 F2 F3 F4 F5 F6 F7 1

storef(base b, off o, f v)

operands: like NoResult [xx]:


Core In Slots Latencies
Silver F0 F1 F2 F3 1
Gold F0 F1 F2 F3 F4 F5 F6 F7 1

storef(p b, off o, s i, scale s, f v)

operands: like NoResult [xx]:


Core In Slots Latencies
Silver F0 F1 F2 F3 1
Gold F0 F1 F2 F3 F4 F5 F6 F7 1

storef(p b, off o, f v)

operands: like NoResult [xx]:


Core In Slots Latencies
Silver F0 F1 F2 F3 1
Gold F0 F1 F2 F3 F4 F5 F6 F7 1

storef(p b, f v, memAttr m)

operands: like NoResult [xx]:


Core In Slots Latencies
Silver F0 F1 F2 F3 1
Gold F0 F1 F2 F3 F4 F5 F6 F7 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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