Difference between revisions of "Instruction Set/rrootu"

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(Created page with "{{DISPLAYTITLE:rrootu}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu block...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Tin/Encoding#753|Tin]] || E0 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
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| [[Cores/Tin/Encoding#rrootu|Tin]] || E0 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
 
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| [[Cores/Copper/Encoding#753|Copper]] || E0 E1 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
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| [[Cores/Copper/Encoding#rrootu|Copper]] || E0 E1 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
 
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| [[Cores/Silver/Encoding#753|Silver]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
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| [[Cores/Silver/Encoding#rrootu|Silver]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
 
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| [[Cores/Gold/Encoding#753|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
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| [[Cores/Gold/Encoding#rrootu|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
 
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| [[Cores/Decimal8/Encoding#753|Decimal8]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
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| [[Cores/Decimal8/Encoding#rrootu|Decimal8]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
 
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| [[Cores/Decimal16/Encoding#753|Decimal16]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
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| [[Cores/Decimal16/Encoding#rrootu|Decimal16]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
 
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:37, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the unsigned integer value domain  

native on: all

reciprocal square root


rrootu(u x) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
Copper E0 E1 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
Silver E0 E1 E2 E3 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
Decimal8 E0 E1 E2 E3 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
Decimal16 E0 E1 E2 E3 b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable