Difference between revisions of "Instruction Set/addux"
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(Created page with "{{DISPLAYTITLE:addux}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream [[Decode|exu block]...") | |||
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| − | + | Excepting unsigned integer add. | |
| + | Overflow produces a [[NaR]]. | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">addux</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#u|u]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">addux</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#u|u]] r<sub>0</sub></code> | ||
Revision as of 10:16, 12 November 2014
realizing exu stream exu block compute phase operation in the unsigned integer value domain using excepting overflow behavior that produces condition codes
aliases: adduxv
native on: all
Excepting unsigned integer add. Overflow produces a NaR.
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 |
| Copper | E0 E1 | 2 |
| Silver | E0 E1 E2 E3 | 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 |
| Decimal8 | E0 E1 E2 E3 | 2 |
| Decimal16 | E0 E1 E2 E3 | 2 |
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 |
| Copper | E0 E1 | 2 |
| Silver | E0 E1 E2 E3 | 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 |
| Decimal8 | E0 E1 E2 E3 | 2 |
| Decimal16 | E0 E1 E2 E3 | 2 |
