Difference between revisions of "Instruction Set/divu"
From Mill Computing Wiki
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{{DISPLAYTITLE:divu}} | {{DISPLAYTITLE:divu}} | ||
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the unsigned integer value domain]] [[Condition Code|that produces condition codes]]<br /> | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the unsigned integer value domain]] [[Condition Code|that produces condition codes]]<br /> | ||
| − | '''native on:''' [[ | + | '''native on:''' [[Cores/Silver|Silver]] <br /> |
</div> | </div> | ||
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</div> | </div> | ||
<br /> | <br /> | ||
| + | |||
| + | {| class="mw-collapsible mw-collapsed wikitable" data-expandtext="▸" data-collapsetext="▾" | ||
| + | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
| + | |- | ||
| + | | [[Cores/Silver/Encoding#divu|Silver]] || E0 || b,b:b=6 bv,bv:bv=6 h,h:h=6 hv,hv:hv=8 w,w:w=6 wv,wv:wv=8 d,d:d=6 dv,dv:dv=8 q,q:q=6 qv,qv:qv=8 | ||
| + | |} | ||
---- | ---- | ||
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</div> | </div> | ||
<br /> | <br /> | ||
| + | |||
| + | {| class="mw-collapsible mw-collapsed wikitable" data-expandtext="▸" data-collapsetext="▾" | ||
| + | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
| + | |- | ||
| + | | [[Cores/Silver/Encoding#divu|Silver]] || E0 || b,b:b=6 bv,bv:bv=6 h,h:h=6 hv,hv:hv=8 w,w:w=6 wv,wv:wv=8 d,d:d=6 dv,dv:dv=8 q,q:q=6 qv,qv:qv=8 | ||
| + | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 00:26, 23 March 2015
speculable exu stream exu block compute phase operation in the unsigned integer value domain that produces condition codes
native on: Silver
Unsigned integer division for quotient.
related operations: remu, divRemu, rdivu, rootu, rrootu
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 | b,b:b=6 bv,bv:bv=6 h,h:h=6 hv,hv:hv=8 w,w:w=6 wv,wv:wv=8 d,d:d=6 dv,dv:dv=8 q,q:q=6 qv,qv:qv=8 |
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 | b,b:b=6 bv,bv:bv=6 h,h:h=6 hv,hv:hv=8 w,w:w=6 wv,wv:wv=8 d,d:d=6 dv,dv:dv=8 q,q:q=6 qv,qv:qv=8 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
