Difference between revisions of "Instruction Set/divRemu"
From Mill Computing Wiki
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{{DISPLAYTITLE:divRemu}} | {{DISPLAYTITLE:divRemu}} | ||
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the unsigned integer value domain]] [[Condition Code|that produces condition codes]]<br /> | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the unsigned integer value domain]] [[Condition Code|that produces condition codes]]<br /> | ||
| − | '''native on:''' [[ | + | '''native on:''' [[Cores/Silver|Silver]] <br /> |
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| + | {| class="mw-collapsible mw-collapsed wikitable" data-expandtext="▸" data-collapsetext="▾" | ||
| + | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
| + | |- | ||
| + | | [[Cores/Silver/Encoding#divRemu|Silver]] || E0 || b,b:b,b=6,6 bv,bv:bv,bv=6,6 h,h:h,h=6,6 hv,hv:hv,hv=6,6 w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=8,8 dv,dv:dv,dv=8,8 q,q:q,q=8,8 qv,qv:qv,qv=8,8 | ||
| + | |} | ||
---- | ---- | ||
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| + | {| class="mw-collapsible mw-collapsed wikitable" data-expandtext="▸" data-collapsetext="▾" | ||
| + | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
| + | |- | ||
| + | | [[Cores/Silver/Encoding#divRemu|Silver]] || E0 || b,b:b,b=6,6 bv,bv:bv,bv=6,6 h,h:h,h=6,6 hv,hv:hv,hv=6,6 w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=8,8 dv,dv:dv,dv=8,8 q,q:q,q=8,8 qv,qv:qv,qv=8,8 | ||
| + | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 00:24, 23 March 2015
speculable exu stream exu block compute phase operation in the unsigned integer value domain that produces condition codes
native on: Silver
Unsigned integer division for quotient and remainder.
related operations: divu, remu, rdivu, rootu, rrootu
divRemu(u x, u y) → u r0, u r1
operands: like DivRem [xx:xx]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 | b,b:b,b=6,6 bv,bv:bv,bv=6,6 h,h:h,h=6,6 hv,hv:hv,hv=6,6 w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=8,8 dv,dv:dv,dv=8,8 q,q:q,q=8,8 qv,qv:qv,qv=8,8 |
divRemu(u x, imm y) → u r0, u r1
operands: like DivRem [xx:xx]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 | b,b:b,b=6,6 bv,bv:bv,bv=6,6 h,h:h,h=6,6 hv,hv:hv,hv=6,6 w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=8,8 dv,dv:dv,dv=8,8 q,q:q,q=8,8 qv,qv:qv,qv=8,8 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
