Difference between revisions of "Instruction Set/shiftluw"

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(Created page with "{{DISPLAYTITLE:shiftluw}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu blo...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#798|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#shiftluw|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#798|Copper]] || E0 || 1
+
| [[Cores/Copper/Encoding#shiftluw|Copper]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#798|Silver]] || E0 E1 || 1
+
| [[Cores/Silver/Encoding#shiftluw|Silver]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#798|Gold]] || E0 E1 || 1
+
| [[Cores/Gold/Encoding#shiftluw|Gold]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#798|Decimal8]] || E0 E1 || 1
+
| [[Cores/Decimal8/Encoding#shiftluw|Decimal8]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#798|Decimal16]] || E0 E1 || 1
+
| [[Cores/Decimal16/Encoding#shiftluw|Decimal16]] || E0 E1 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#797|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#shiftluw|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#797|Copper]] || E0 || 1
+
| [[Cores/Copper/Encoding#shiftluw|Copper]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#797|Silver]] || E0 E1 || 1
+
| [[Cores/Silver/Encoding#shiftluw|Silver]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#797|Gold]] || E0 E1 || 1
+
| [[Cores/Gold/Encoding#shiftluw|Gold]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#797|Decimal8]] || E0 E1 || 1
+
| [[Cores/Decimal8/Encoding#shiftluw|Decimal8]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#797|Decimal16]] || E0 E1 || 1
+
| [[Cores/Decimal16/Encoding#shiftluw|Decimal16]] || E0 E1 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   using widening overflow behavior   that produces condition codes

native on: all

bitwise shift

shiftluw(u x, bit bits) → u r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 1
Copper E0 1
Silver E0 E1 1
Gold E0 E1 1
Decimal8 E0 E1 1
Decimal16 E0 E1 1

shiftluw(u x, n bits) → u r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 1
Copper E0 1
Silver E0 E1 1
Gold E0 E1 1
Decimal8 E0 E1 1
Decimal16 E0 E1 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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