Difference between revisions of "Instruction Set/addux"
From Mill Computing Wiki
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{{DISPLAYTITLE:addux}} | {{DISPLAYTITLE:addux}} | ||
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the unsigned integer value domain]] [[Overflow|using excepting overflow behavior]] [[Condition Code|that produces condition codes]]<br /> | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the unsigned integer value domain]] [[Overflow|using excepting overflow behavior]] [[Condition Code|that produces condition codes]]<br /> | ||
| − | '''aliases:''' | + | '''aliases:''' addux2 <br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding#addux|Tin]] || E0 || | + | | [[Cores/Tin/Encoding#addux|Tin]] || E0 || |
|- | |- | ||
| − | | [[Cores/Copper/Encoding#addux|Copper]] || E0 | + | | [[Cores/Copper/Encoding#addux|Copper]] || E0 || |
|- | |- | ||
| − | | [[Cores/Silver/Encoding#addux|Silver]] || E0 E1 E2 E3 || | + | | [[Cores/Silver/Encoding#addux|Silver]] || E0 E1 E2 E3 || |
|- | |- | ||
| − | | [[Cores/Gold/Encoding#addux|Gold]] || E0 | + | | [[Cores/Gold/Encoding#addux|Gold]] || E0 || |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
|} | |} | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding#addux|Tin]] || E0 || | + | | [[Cores/Tin/Encoding#addux|Tin]] || E0 || |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
|- | |- | ||
| − | | [[Cores/ | + | | [[Cores/Copper/Encoding#addux|Copper]] || E0 || |
|- | |- | ||
| − | | [[Cores/ | + | | [[Cores/Silver/Encoding#addux|Silver]] || E0 E1 E2 E3 || |
|- | |- | ||
| − | | [[Cores/ | + | | [[Cores/Gold/Encoding#addux|Gold]] || E0 || |
|} | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 13:57, 23 February 2021
speculable exu stream exu block compute phase operation in the unsigned integer value domain using excepting overflow behavior that produces condition codes
aliases: addux2
native on: all
Excepting unsigned integer add. Overflow produces a NaR.
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 E2 E3 | |
| Gold | E0 |
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 E2 E3 | |
| Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
