Difference between revisions of "Instruction Set/shiftluw"
From Mill Computing Wiki
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<code style="font-size:130%"><b style="color:#050">shiftluw</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) → [[Domains#u|u]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">shiftluw</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) → [[Domains#u|u]] r<sub>0</sub></code> | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands# | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidening|like Widening xx:2x]] |
</div> | </div> | ||
<br /> | <br /> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding#shiftluw|Tin]] || E0 || | + | | [[Cores/Tin/Encoding#shiftluw|Tin]] || E0 || |
|- | |- | ||
| − | | [[Cores/Copper/Encoding#shiftluw|Copper]] || E0 || | + | | [[Cores/Copper/Encoding#shiftluw|Copper]] || E0 || |
|- | |- | ||
| − | | [[Cores/Silver/Encoding#shiftluw|Silver]] || E0 E1 || | + | | [[Cores/Silver/Encoding#shiftluw|Silver]] || E0 E1 || |
|- | |- | ||
| − | | [[Cores/Gold/Encoding#shiftluw|Gold]] || E0 | + | | [[Cores/Gold/Encoding#shiftluw|Gold]] || E0 || |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
|} | |} | ||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">shiftluw</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#n|n]]</span> <span title="belt operand from ops window">bits</span>) → [[Domains#u|u]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">shiftluw</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#n|n]]</span> <span title="belt operand from ops window">bits</span>) → [[Domains#u|u]] r<sub>0</sub></code> | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands# | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidening|like Widening xx:2x]] |
</div> | </div> | ||
<br /> | <br /> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding#shiftluw|Tin]] || E0 || | + | | [[Cores/Tin/Encoding#shiftluw|Tin]] || E0 || |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
|- | |- | ||
| − | | [[Cores/ | + | | [[Cores/Copper/Encoding#shiftluw|Copper]] || E0 || |
|- | |- | ||
| − | | [[Cores/ | + | | [[Cores/Silver/Encoding#shiftluw|Silver]] || E0 E1 || |
|- | |- | ||
| − | | [[Cores/ | + | | [[Cores/Gold/Encoding#shiftluw|Gold]] || E0 || |
|} | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 13:26, 23 February 2021
speculable exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes
native on: all
Unsigned bitwise left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get zero extended in the widening.
shiftluw(u x, bit bits) → u r0
operands: like Widening xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 | |
| Gold | E0 |
operands: like Widening xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 | |
| Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
