Difference between revisions of "Instruction Set/call1"

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| [[Cores/Tin/Encoding#call1|Tin]] || F0 || 1
 
| [[Cores/Tin/Encoding#call1|Tin]] || F0 || 1
 
|-
 
|-
| [[Cores/Copper/Encoding#call1|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#call1|Copper]] || F0 || 1
 
|-
 
|-
 
| [[Cores/Silver/Encoding#call1|Silver]] || F0 F1 F2 || 1
 
| [[Cores/Silver/Encoding#call1|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
| [[Cores/Gold/Encoding#call1|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#call1|Gold]] || F0 || 1
|-
+
| [[Cores/Decimal8/Encoding#call1|Decimal8]] || F0 F1 F2 || 1
+
|-
+
| [[Cores/Decimal16/Encoding#call1|Decimal16]] || F0 F1 F2 || 1
+
 
|}
 
|}
  
Line 69:Line 65:
 
| [[Cores/Tin/Encoding#call1|Tin]] || F0 || 1
 
| [[Cores/Tin/Encoding#call1|Tin]] || F0 || 1
 
|-
 
|-
| [[Cores/Copper/Encoding#call1|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#call1|Copper]] || F0 || 1
 
|-
 
|-
 
| [[Cores/Silver/Encoding#call1|Silver]] || F0 F1 F2 || 1
 
| [[Cores/Silver/Encoding#call1|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
| [[Cores/Gold/Encoding#call1|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#call1|Gold]] || F0 || 1
|-
+
| [[Cores/Decimal8/Encoding#call1|Decimal8]] || F0 F1 F2 || 1
+
|-
+
| [[Cores/Decimal16/Encoding#call1|Decimal16]] || F0 F1 F2 || 1
+
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:12, 23 February 2021

realizing  flow stream  flow block  call phase   operation  

native on: all

Call function with one return value.

An optimization for the common case of one return value functions. There are only gang encodings of this, for functions with more arguments than the one slot call operations can accomodate.

As with all ganged call operations, the target address is always in the last gang slot.

related operations: calltr1, callfl1, retn


call1(p target, args args) → op r

operands: like Inv :


encoding: call1(op q, off target, count argc) , call1(op q, off target, count argc, lit argv) , call1(op q, off target, count argc, lit argv, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 F1 F2 1
Gold F0 1

call1(lbl target, args args) → op r

operands: like Inv :


encoding: call1(off target, count argc) , call1(off target, count argc, lit argv) , call1(off target, count argc, lit argv, lit argv) , call1(off target, count argc, lit argv, lit argv, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 1
Silver F0 F1 F2 1
Gold F0 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable