Difference between revisions of "Instruction Set/calln"

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(Created page with "{{DISPLAYTITLE:calln}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  flow stream Decode|flow bloc...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Tin/Encoding#948|Tin]] || F0 || 1
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| [[Cores/Tin/Encoding#calln|Tin]] || F0 || 1
 
|-
 
|-
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| [[Cores/Copper/Encoding#948|Copper]] || F0 F1 || 1
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| [[Cores/Copper/Encoding#calln|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#948|Silver]] || F0 F1 F2 || 1
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| [[Cores/Silver/Encoding#calln|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#948|Gold]] || F0 F1 F2 F3 || 1
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| [[Cores/Gold/Encoding#calln|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#948|Decimal8]] || F0 F1 F2 || 1
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| [[Cores/Decimal8/Encoding#calln|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#948|Decimal16]] || F0 F1 F2 || 1
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| [[Cores/Decimal16/Encoding#calln|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#949|Tin]] || F0 || 1
+
| [[Cores/Tin/Encoding#calln|Tin]] || F0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#949|Copper]] || F0 F1 || 1
+
| [[Cores/Copper/Encoding#calln|Copper]] || F0 F1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#949|Silver]] || F0 F1 F2 || 1
+
| [[Cores/Silver/Encoding#calln|Silver]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#949|Gold]] || F0 F1 F2 F3 || 1
+
| [[Cores/Gold/Encoding#calln|Gold]] || F0 F1 F2 F3 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#949|Decimal8]] || F0 F1 F2 || 1
+
| [[Cores/Decimal8/Encoding#calln|Decimal8]] || F0 F1 F2 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#949|Decimal16]] || F0 F1 F2 || 1
+
| [[Cores/Decimal16/Encoding#calln|Decimal16]] || F0 F1 F2 || 1
 
|}
 
|}
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 +
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  flow stream  flow block  call phase   operation  

native on: all

function call

calln(lit n, p target, args args) → ops r0 ...rn

operands: like Inv :


encoding: calln(lit n, p target, off argv, count argc) , calln(lit n, p target, off argv, count argc, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

calln(lit n, lbl target, args args) → ops r0 ...rn

operands: like Inv :


encoding: calln(lit n, off target, count argc) , calln(lit n, off target, count argc, lit argv) , calln(lit n, off target, count argc, lit argv, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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