Difference between revisions of "Instruction Set/subuw"

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(Created page with "{{DISPLAYTITLE:subuw}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|exu block]...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#873|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Tin/Encoding#subuw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#873|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
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| [[Cores/Copper/Encoding#subuw|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#873|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Silver/Encoding#subuw|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#873|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Gold/Encoding#subuw|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#873|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Decimal8/Encoding#subuw|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#873|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Decimal16/Encoding#subuw|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#874|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Tin/Encoding#subuw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#874|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Copper/Encoding#subuw|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#874|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Silver/Encoding#subuw|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#874|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Gold/Encoding#subuw|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#874|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Decimal8/Encoding#subuw|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#874|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
+
| [[Cores/Decimal16/Encoding#subuw|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2  
 
|}
 
|}
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   using widening overflow behavior   that produces condition codes

native on: all

subtraction

subuw(u x, u y) → u r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Copper E0 E1 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Silver E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Decimal8 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Decimal16 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2

subuw(u x, imm y) → u r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Copper E0 E1 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Silver E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Gold E0 E1 E2 E3 E4 E5 E6 E7 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Decimal8 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2
Decimal16 E0 E1 E2 E3 b,b:h=1 h,h:w=1 w,w:d=1 d,d:q=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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