Difference between revisions of "Instruction Set/xorl"

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(Created page with "{{DISPLAYTITLE:xorl}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream  exu block...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#915|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#xorl|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#915|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#xorl|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#915|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#xorl|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#915|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#xorl|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#915|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#xorl|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#915|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#xorl|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#916|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#xorl|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#916|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#xorl|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#916|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#xorl|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#916|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#xorl|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#916|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#xorl|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#916|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#xorl|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain   that produces condition codes

aliases: xorls xorlu
native on: all

bitwise exclusive or

xorl(op x, op y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1

xorl(op x, imm y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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