Difference between revisions of "Instruction Set/narrowfz"

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(Created page with "{{DISPLAYTITLE:narrowfz}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu blo...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Silver/Encoding#663|Silver]] || E0 E1 || w:h=3 d:w=4 q:d=5  
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| [[Cores/Silver/Encoding#narrowfz|Silver]] || E0 E1 || w:h=3 d:w=4 q:d=5  
 
|-
 
|-
| [[Cores/Gold/Encoding#663|Gold]] || E0 E1 E2 E3 || w:h=3 d:w=4 q:d=5  
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| [[Cores/Gold/Encoding#narrowfz|Gold]] || E0 E1 E2 E3 || w:h=3 d:w=4 q:d=5  
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Silver/Encoding#664|Silver]] || E0 E1 || wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5  
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| [[Cores/Silver/Encoding#narrowfz|Silver]] || E0 E1 || wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5  
 
|-
 
|-
| [[Cores/Gold/Encoding#664|Gold]] || E0 E1 E2 E3 || wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5  
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| [[Cores/Gold/Encoding#narrowfz|Gold]] || E0 E1 E2 E3 || wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5  
 
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:36, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the binary floating point value domain  

native on: Silver Gold

narrow scalar to half width


narrowfz(f v) → f r0

operands: like Narrowf [ff:½f]


Core In Slots Latencies
Silver E0 E1 w:h=3 d:w=4 q:d=5
Gold E0 E1 E2 E3 w:h=3 d:w=4 q:d=5

narrowfz(f v1, f v2) → f r0

operands: like Narrowvf [FF:½F]


Core In Slots Latencies
Silver E0 E1 wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5
Gold E0 E1 E2 E3 wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable