Difference between revisions of "Instruction Set/rd"

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m (Protected "Instruction Set/rd": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
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{{DISPLAYTITLE:rd}}
 
{{DISPLAYTITLE:rd}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|reader block]]&nbsp;&nbsp;[[Phasing|reader phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|reader block]]&nbsp;&nbsp;[[Phasing|reader phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>

Revision as of 09:30, 9 February 2015

speculable  exu stream  reader block  reader phase   operation   in the logical value domain  

native on: all

hardware reader


rd(const src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 0
Copper R0 R1 0
Silver R0 R1 R2 R3 R4 R5 0
Gold R0 R1 R2 R3 R4 R5 R6 R7 0
Decimal8 R0 R1 R2 R3 R4 R5 0
Decimal16 R0 R1 R2 R3 R4 R5 0

rd(scratch src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 0
Copper R0 R1 0
Silver R0 R1 R2 R3 R4 R5 0
Gold R0 R1 R2 R3 R4 R5 R6 R7 0
Decimal8 R0 R1 R2 R3 R4 R5 0
Decimal16 R0 R1 R2 R3 R4 R5 0

rd(reg src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 0
Copper R0 R1 0
Silver R0 R1 R2 R3 R4 R5 0
Gold R0 R1 R2 R3 R4 R5 R6 R7 0
Decimal8 R0 R1 R2 R3 R4 R5 0
Decimal16 R0 R1 R2 R3 R4 R5 0

rd(stream src)

operands: like NoArgs :[x]


Core In Slots Latencies
Tin R0 R1 0
Copper R0 R1 0
Silver R0 R1 R2 R3 R4 R5 0
Gold R0 R1 R2 R3 R4 R5 R6 R7 0
Decimal8 R0 R1 R2 R3 R4 R5 0
Decimal16 R0 R1 R2 R3 R4 R5 0


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