Difference between revisions of "Encoding"
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| − | The Mill architecure employ a unique split stream instruction encoding that | + | The Mill architecure employ a unique split stream instruction encoding that though being wide issue and very dense enables sustained decoding rates of over 30 operations per cycle. As it provides those unparalleled numbers, it does so at the fraction of the energy and transistor cost of mainstream variable instruction length instruction sets like x86. |
== Semantics == | == Semantics == | ||
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=== <span id="instructions">Instructions and Operations and Bundles</span> === | === <span id="instructions">Instructions and Operations and Bundles</span> === | ||
| − | The unusual encoding makes it necessary make clear distincitons between instructions and operations and bundles that are not really necessary on traditional machines. In the earliest <abbr title="Reduced Instructions Set Computer">RISC</abbr> architectures an instruction and an operation and a bundle are usually the same thing: a word size bundle of bits is retrieved from the a | + | The unusual encoding makes it necessary make clear distincitons between instructions and operations and bundles that are not really necessary on traditional machines. In the earliest <abbr title="Reduced Instructions Set Computer">RISC</abbr> architectures an instruction and an operation and a bundle are usually the same thing: a word size bundle of bits is retrieved from the a highest instruction cache line and dropped into the decoder. There one instruction is retrieved and issued resulting in one operation being performed. On wide issue machines one instruction can contain several operations that are all issued together. Modern machines drop a bundle containing several instructions at once into the decoder. |
So, a bundle is the batch of memory that gets dropped into the decoder together.<br /> | So, a bundle is the batch of memory that gets dropped into the decoder together.<br /> | ||
Revision as of 15:15, 25 July 2014
The Mill architecure employ a unique split stream instruction encoding that though being wide issue and very dense enables sustained decoding rates of over 30 operations per cycle. As it provides those unparalleled numbers, it does so at the fraction of the energy and transistor cost of mainstream variable instruction length instruction sets like x86.
Contents
Semantics
Extended Basic Block
Code on the Mill is organised into EBBs, i.e. batches of code with one entry point and one or more exit points. There is no implicit fallthrough in EBBs, the instruction flow can only leave them with an explicit branch, which means at least the last operation in every EBB is a branch.
Instructions and Operations and Bundles
The unusual encoding makes it necessary make clear distincitons between instructions and operations and bundles that are not really necessary on traditional machines. In the earliest RISC architectures an instruction and an operation and a bundle are usually the same thing: a word size bundle of bits is retrieved from the a highest instruction cache line and dropped into the decoder. There one instruction is retrieved and issued resulting in one operation being performed. On wide issue machines one instruction can contain several operations that are all issued together. Modern machines drop a bundle containing several instructions at once into the decoder.
So, a bundle is the batch of memory that gets dropped into the decoder together.
An instruction is all the operations that get issued to the functional units together.
And an operation is the most basic piece of processing in a functional unit, an add or xor for example.
Split Instruction Streams
Bit Format
Rationale
Implementation
See Also
Decode, Phasing, Instruction Set
