Difference between revisions of "Instruction Set/f2sefxp"
From Mill Computing Wiki
m (Protected "Instruction Set/f2sefxp": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite))) | |||
Line 1: | Line 1: | ||
{{DISPLAYTITLE:f2sefxp}} | {{DISPLAYTITLE:f2sefxp}} | ||
− | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Overflow|using excepting overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward positive infinity]]<br /> |
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br /> | '''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br /> | ||
</div> | </div> |
Latest revision as of 09:29, 9 February 2015
speculable exu stream exu block compute phase operation in the binary floating point value domain using excepting overflow behavior that produces condition codes and rounds toward positive infinity
Exactly convert a binary floating point value to a signed integer, rounding toward positive infinity and producing NaRs on overflow.
operands: like Addf [ff:f]
Core | In Slots | Latencies |
---|---|---|
Silver | E0 E1 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Gold | E0 E1 E2 E3 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable