Difference between revisions of "Instruction Set/mulsw"

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m (Protected "Instruction Set/mulsw": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
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{{DISPLAYTITLE:mulsw}}
 
{{DISPLAYTITLE:mulsw}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>

Revision as of 09:29, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Signed Integer multiply. Widening.


mulsw(s x, s y) → s r0

operands: like Widen xx:2x


Core In Slots Latencies
Tin E0 b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6
Copper E0 b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6
Silver E0 E1 b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6
Gold E0 E1 E2 E3 b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6
Decimal8 E0 E1 b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6
Decimal16 E0 E1 b,b:h=3 h,h:w=4 w,w:d=5 d,d:q=6


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable