Difference between revisions of "Instruction Set/shiftluwv"

Revision as of 10:36, 11 January 2015

realizing exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes

native on: all

Unsigned bitwise vector left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get zero extended in the widening. Produces two result vectors.

shiftluwv(u x, bit bits) → u r₀, u r₁

operands: like Widenv XX:2X2X

Core	In Slots	Latencies
Tin	E0	2 2
Copper	E0	2 2
Silver	E0 E1	2 2
Gold	E0 E1	2 2
Decimal8	E0 E1	2 2
Decimal16	E0 E1	2 2

shiftluwv(u x, n bits) → u r₀, u r₁

operands: like Widenv XX:2X2X

Core	In Slots	Latencies
Tin	E0	2 2
Copper	E0	2 2
Silver	E0 E1	2 2
Gold	E0 E1	2 2
Decimal8	E0 E1	2 2
Decimal16	E0 E1	2 2

Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Difference between revisions of "Instruction Set/shiftluwv"

Revision as of 10:36, 11 January 2015

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@@ Line 4: / Line 4: @@
 </div>
-bitwise shift
+Unsigned bitwise vector left shift. Widening.
+The bit count by which to shift is an unsigned number.
+The higher order bits get zero extended in the widening.
+Produces two result vectors.
 ----
 <code style="font-size:130%"><b style="color:#050">shiftluwv</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) &#8594; [[Domains#u|u]] r<sub>0</sub>, [[Domains#u|u]] r<sub>1</sub></code>